1. Field of the Invention
The present invention relates in general to systems for modeling the logic and behavior of electronic circuits, and in particular to a system for characterizing an electronic circuit in a manner that graphically correlates its logic to its behavior.
2. Description of Related Art
A circuit designer can model an integrated circuit in several ways. For example FIG. 1 illustrates a schematic diagram modeling one small module MOD1 of an intigrated circuit. The schematic diagram models the logic of module MOD1 indicating that it includes AND gates 10–12, OR gates 14–15 and six registers 17–22 and showing how the parts are interconnected. The schematic diagram also labels the various input, output and internal signals and shows how they are logically related by using symbols to represent OR, AND and register logic operations. While the schematic diagram does not directly indicate how any of the signals the circuit generates would behave in response to particular input signal patterns, it provides enough information to enable a design engineer to determine the signal behavior. However since it is usually hard to figure out how even simple circuits would respond over a long period of time to various input signal patterns, designers normally use computer-based circuit simulators to do the job for them.
To use a circuit simulator a designer creates a different kind of circuit model in a form that is understood by the circuit simulator. FIG. 2 illustrates the source code of a hardware description language (HDL) or “netlist” model of the MOD1 circuit of FIG. 1. The netlist names the module and the various input, output and internal signals, indicates the bit width of each signal, and defines logical relationships between the signals.
Thus the schematic diagram of FIG. 1 and the netlist of FIG. 2 convey generally similar information about module MOD1, though in a different format. Note that these are logic models of module MOD1, not behavioral models. A logic model describes a circuit in terms of its logical structure while a behavioral model describes the circuit in terms of how its various output and internal signals change over time in response to a particular pattern of input signals. Although a human or a circuit simulator can deduce how module MOD1 might respond over time to various input signal patterns based on information presented by those models, the schematic and netlist models themselves do not directly represent the temporal behavior of the signals the module generates in response to its input signals. Designers use other kinds of models to represent the behavior of a circuit. Indeed the primary purpose of a circuit simulator is to convert a logic model of a circuit into a behavioral model of the circuit.
FIG. 3 is a block diagram illustrating a conventional circuit simulator 23 receiving a netlist 24 and a “test bench” 26 as input and producing an output waveform data 28 describing the behavior of various input, output or internal signals of the circuit modeled by the netlist. The circuit designer typically creates the test bench 26 containing code describing the behavior of the circuit input signals as functions of time and specifying initial states of the circuit's internal data storage elements. Test bench 26 also indicates which circuit input, output and/or internal signals are to be represented by waveform, data 28, and specifies parameters controlling the accuracy, duration and other aspects of the simulation. The waveform, data 28 simulator 23 produces includes a set of data sequences, each representing the magnitude of a separate circuit input, output or internal signal as a function of time.
A simulator's output waveform data 26 is often converted into a more comprehensible graphical form when a user 29 wants to view the results of the simulation. Hence most simulators include a display controller 30 for converting waveform data 38 into a waveform display 32 graphically depicting various circuit signals as functions of time.
FIG. 4 illustrates an example waveform display 32 that display controller 30 of FIG. 3 could produce from the output waveform data produced by circuit simulator 32 when simulating circuit module MOD1 of FIG. 1. Waveform display 32 illustrates the behavior of register output signals R1–R6, input signals IN1 and IN2 and output signal OUT as functions of time over a period between time 0 and 100 nanoseconds (ns) when clock signal CK1 has a period of 10 ns. Waveform display 32 could also depict the behavior of one or more of the circuits internal signals S1–S5. User 29 (FIG. 3) normally controls the waveform display, for example by telling display controller 30 which waveforms are to be displayed, adjusting the horizontal scale of the waveform display, and choosing the particular span of simulation time depicted in the waveform display.
The waveform data output 28 of simulator 23 and waveform display 32 of FIG. 4 are behavior models of the circuit because they describe the behavior of the signals the circuit generates in response to particular patterns of input signals. However these are not logic models because they do not tell us anything about the structure of the circuit that makes those signals behave that way. Note that the waveform display of FIG. 4 lacks any information about the logic of the circuit module that produced the R1–R6 signals in response to the IN1, IN2 and CK1 signals. Hence a design engineer trying to determine why signal R1 went high instead of staying low at time 90 cannot do so simply by inspecting the waveform display of FIG. 4. He or she must instead return to a logic model of the circuit, such as the schematic model of FIG. 1 or the netlist model of FIG. 2, because those models define the logic relating the behavior of the various signals. Looking at both the logic model of FIG. 1 and the behavioral model of FIG. 4, the design engineer could determine, for example, that if the R1 signal as to stay low at time SO, then at least one of the R2 and R3 signals should have been low at time 90 when the CK1 signal clocked register 17. The design engineer might also have been able to determine, for example, that the R2 signal would have been low at time 90 if either the R4 signal or the R5 signal had been low at time 80 when the CLK1 signal clocked registers 20 and 21.
That type of analysis helps design engineers to pinpoint logic errors in a circuit design, but they often find such analysis difficult because it requires them to correlate two different circuit models, the behavioral model of FIG. 4 and the logic model of FIG. 1 or 2. Since the example module MOD1 is a relatively simple circuit, it is not too difficult to determine the chain of events that lead to the R1 signal going high at time 90. However it can be hard for a design engineer to relate the behavior and logic models when the circuit being modeled is large and complex. When a design engineer is trying to figure out why a particular signal behaves as it does in a behavior model, the logic model he or she studies for an answer can in some sense present too much information. It includes not only the circuit logic that affects the signal of interest, it also shows circuit logic that may have no influence on the signal of interest. The portions of the logic model that do not influence a signal of interest obscure the relevant portions of the model that do.
The problem of relating circuit behavior to circuit logic compounds as the design engineer looks farther backward in time from a circuit event of interest to determine the logical cause of the event. For example if signal R1 went high at time 90 because the R2 and R3 signals went high at time 80, then a design engineer might like to know why the R2 and R3 signals went high at time 80. By perusing the schematic and the waveform display he or she can determine that the states of the R1, R4 and R5 signals at time 70 determine the states of the R2 and R3 signals at time 80. However as the design engineer goes farther back time looking for signal events having an influence on the signal event occurring at time 90 the number of signal events that must be considered grows and the logic involved can become quite complicated, particularly when the circuit includes feedback loops. Similarly when the design engineer wants to determine, for example, how a state change in the R6 signal at time 10 might have affected states of various signals thereafter, the logical relationship between that R6 signal state change and a state change in other signals many clock cycles later can be very complex and difficult to determine from the circuit schematic, particularly where the circuit includes feedback.
What is needed is a system for characterizing both the logic and the behavior of a circuit in a way that makes it easier for a design engineer to analyze the circuit to understand the logical causes and effects of various signal events.